Micron Lays Out Its 2027 Memory Plan and Rejects Rivals' Chip Design
Wednesday, October 218 Min Read
Micron technology chief Scott DeBoer set out DRAM, NAND and HBM plans through 2027 and said the 4F² design that CXMT is adopting this year and Samsung is expected to adopt in 2028 has fundamental problems. New AI memory uses more silicon per bit, keeping supply tight for two more years.
2H 2027
New DRAM and NAND Production
~25%
Density Gain on the New DRAM Node
400+
Layers in G11 NAND
Over 4x
HBM4E Silicon Per Bit
In This Piece5 Sections
Micron president and chief technology officer Scott DeBoer walked analysts through the company's technology roadmap on Wednesday morning. His sharpest line was aimed at a rival design: he said the DRAM layout known as 4F² has fundamental problems.
The second message was about supply. DeBoer said new memory types built for AI consume more silicon per bit, which squeezes supply of conventional memory even further.
Micron has not published the slides, so the details below rely on Stocktwits' account of the call.
Micron's 2027 Plan: New DRAM, G11 NAND and Vertical HBM
The new DRAM node will enter production in the second half of 2027 at Micron's Boise fab. Reported as 1-delta, the node raises bit density by roughly 25%. Samsung is reportedly targeting late 2027 for its equivalent node.
In NAND, Micron is skipping a generation and moving to G11. The chip has more than 400 layers, twice the density of G9 and 1.5 times its data speed, and ramps in the same window.
HBM4, high-bandwidth memory, is in volume production and moves 2.8 terabytes per second per stack. DeBoer said about 100 such stacks roughly equal the world's total internet bandwidth.
The new product is vertical HBM, which stacks memory directly on top of the processor rather than beside it. DeBoer said hybrid bonding, which joins layers without solder, is essential for it. Micron ranks third in HBM; Counterpoint put second-quarter shares at SK Hynix 50%, Samsung 33% and Micron 18%.
The 4F² Debate: Micron Breaks With Its Rivals
In DRAM, each bit is an electric charge held in a tiny capacitor. 4F² packs cells more tightly than today's 6F² layout, using 33% less area per cell.
DeBoer said density is limited by the spacing between capacitors, not by the cell's shape. He called 4F²'s advantage "a bit of a myth": "There's fundamental problems with 4F squared scaling."
Micron says it has studied the design for two decades but chose not to commercialize it because of cost and complexity. Its alternative is 3D DRAM, stacking cells in layers, on a timeline set by economics.
Açılış Zili covered CXMT's 4F² move on Oct. 12, and Samsung is expected to adopt the design in 2028. If Micron is right, the route to higher density without EUV machines is narrower than it looks on paper.
The market heard the webinar as a product launch. The real news was on the supply side.
Why New Memory Uses More Silicon
Micron CEO Sanjay Mehrotra said in March 2025 that HBM3E uses three times the silicon of DDR5 for the same number of bits. He added that the ratio would rise with HBM4 and exceed four to one with HBM4E. DeBoer said Wednesday that vertical products push the multiple higher still.
That is why Micron expects industry DRAM bit supply to grow in the low 20% range in both 2027 and 2028, and still fall short of demand. The company has already contracted the vast majority of its 2027 HBM supply at sharply higher prices.
The shortage shows up in pricing. Micron's gross margin reached 87% last quarter, and it guides to $61.5B of revenue for the September-November quarter.
Shares Sold Before the Webinar, and a Strike in Taiwan
Timeline
- July 17DeBoer adopts a 10b5-1 trading plan.
- September 30Micron guides to $61.5B quarterly revenue.
- October 10CXMT announces its 4F² server memory plan.
- October 16DeBoer sells 28,545 shares near $900.
- October 21Webinar sets out the 2027 roadmap and 4F² critique.
- October 22Taoyuan union holds a one-day strike.
DeBoer's Oct. 16 sale totaled about $25.7M and left him with 147,430 shares. His Form 4 filing with the SEC shows the sale ran under a 10b5-1 plan adopted on July 17.
Such plans fix sale dates and terms months ahead, so executives cannot time trades on later information. More: Insider Trading.
The second risk is in Taiwan. The union at Micron's Taoyuan fab, which makes DRAM and HBM, plans a one-day warning strike on October 22, backed by 1,994 of 2,012 votes. It wants 15% of operating profit; the Taichung union has already signed a deal.
The stock traded at $916.88 on Wednesday afternoon, up 2.3%. The gain began premarket, before the webinar, and was tied to the Taichung deal; nothing shows the presentation moved the price on its own. The chart below shows the path since the $1,255 peak in June.
What It Means for Investors
- The market did not price the 2027 timeline; the stock started rising before the webinar, on the Taiwan labor deal.
- A rising silicon multiple tightens conventional DRAM supply, which means pricing power for Micron, SK Hynix and Samsung and higher costs for server makers buying memory.
- The threshold to watch is the second half of 2027: if the new DRAM node reaches volume in Boise before Samsung's late-2027 target, Micron enters the HBM5 race ahead.
- The risk to the thesis is that rivals betting on 4F² gain density faster than Micron expects; Micron's 3D DRAM path still has no date.
Because Micron has not published slides, the webinar content relies on Stocktwits' Oct. 21 account of the call, including DeBoer's quotes. Financials and the supply outlook come from Micron's Sept. 30 earnings remarks, the share sale from DeBoer's SEC Form 4, the strike from Reuters and Focus Taiwan, the 2025 silicon ratio from an earnings call quoted by Blocks and Files, and market share from Counterpoint.
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